N V RAJESH KUMAR M                                   

Academic Background:  

·         M.Tech in Energy Sciences and Engineering from I.I.T. Bombay, Mumbai in 2010

·         B.E. in Electrical and Electronics Engineering from S.R.K.R. Engineering College, Bhimavaram (Andhra Pradesh)

·         Diploma in Electrical and Electronics Engineering from Govt. Polytechnic, Vijayawada (Andhra Pradesh)  

Work Experience: 

·         Solar Photovoltaic System Engineer at BHEL - Electronics Division, Bangalore since July 2010  

  Contact# +91-8867775422

  Email id: hotcool030@gmail.com  

  Research Interests: Solar Photovoltaics

  Project: Electrical Simulation of Defects in Thin-film Crystalline Silicon Solar Cells

 Simulations are done on thin-film crystalline (CSG) silicon solar cells to know the effect of various types of defects on module performance parameters like fill factor and maximum power output and the physical origin of these defects. Dark Lock-in Thermography (DLIT) has been used to investigate some of these defects and from the DLIT images, temperature modulations of the shunt affected areas can be correlated with the potential distribution of those defected areas in the images obtained from potential mapping technique. DLIT images also reveal about the type of the defects and its physical origin. This analysis helps us to know the severity of the shunts in module performance, its physical origin and also how it affects the potential distribution over the module.